Nvidia Recruitment Drive; Hiring Verification Engineer – Apply Now

They are now looking for a Verification Engineer - Memory Subsystem. NVIDIA is seeking passionate, highly motivated, and innovative verification engineers to join the Graphics Engineering team working on the verification of powerful memory subsystem IPs used in their industry-leading Graphics Processors. This position offers the opportunity to have a real impact in a dynamic, technology-focused company creating ripples in the field of artificial intelligence with ground breaking product lines ranging from data centers to consumer graphics and self-driving cars. They have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

Name of the Organization: Nvidia

Requisition ID: JR1990029

Positions: Verification Engineer - Memory Subsystem

Location: Bengaluru

Salary: As per company Norms

Educational Qualifications:

• BS /MS in EE/ECE with 2+ years of experience
• Exposure to verification closure of complex IP/sub-system for at least one project
• Expertise in industry-standard verification flows like SV random testing, UVM, FV, coverage metrics, profiling tools, X prop, etc.
• Strong coding skills in SV
• Passion for debugging and good problem solving skills
• Strong communication and interpersonal skills

Ways to stand out from the crowd:

• Prior verification experience related to memory subsystem/network interconnect IPs is a huge plus
• Familiarity with memory subsystem concepts such as cache coherency, memory consistency models, arbitration policies, high-speed IO protocols and/or on-chip interconnect
• Familiar with scripting languages (Perl/python).

Responsibilities:

• Responsibility includes verifying the design, architecture and micro-architecture using sophisticated verification methodologies
• Work on the development of the verification infrastructure components (functional models/scoreboards/setting up new verification environments) for complex IPs using UVM methodology
• Define the verification scope, develop testplans and work on functional coverage driven verification closure
• Collaborate with architects, designers, software engineers, post-silicon teams across sites for innovative and timely solutions

 

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